A4. Asynchronous Communication Interface Adapter 6551 (from Synertek data sheet) ----------------------------------------------------- Features - on-chip baud generator: 15 programmable baud rates derived from a standard 1.8432 MHz external crystal (50 to 19,200 baud) - external 16x clock input for non-standard baud rates (up to 125Kbaud) - programmable interrupt and status register - programmable: word lengths, number of stop bits, parity bit generation and detection - parity: odd, even, none, mark, space - data set and modem control signals provided - full-duplex or half-duplex operation Interface description - the TxD (Transmit Data) output line is used to transfer serial NRZ (non-return-to-zero) data to the modem. The LSB (Least Significant Bit) of the Transmit Data Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected. - the RxD (Receive Data) input line is used to transfer serial NRZ data into the ACIA from the modem, LSB first. The receiver data rate is either the programmed baud rate or the rate of an externally generated receiver clock. This selection is made by programming the Control Register. - the RTS (Request To Send, active low) output pin is used to control the modem from the processor. The state of the RTS pin is determined by the contents of the Command Register - the CTS (Clear To Send, active low) input pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter is automatically disabled if CTS is high. - the DTR (Data Terminal Ready, active low) output pin is used to indicate the status of the 6551 to the modem. A low on DTR indicates the 6551 is enabled and a high indicates it is disabled. The processor controls this pin via bit 0 of the Command Register. - the DSR (Data Set Ready, active low) input pin is used to indicate to the 6551 the status of the modem. A low indicates the ready state and a high, not ready. If Command Register bit 0 = 1 and a change of state on DSR occurs, IRQ will be set, and status register bit 6 will reflect the new level. The state of DSR does not affect either Transmitter or Receiver operation. - the DCD (Data Carrier Detect, active low) input pin is used to indicate to the 6515 the status of the carrier-detect output of the modem. A low indicates that the modem carrier signal is present, and a high, that it is not. If Command Register bit 0 = 1 and a change of state on DCD occurs, IRQ will be set, and status register bit 5 will reflect the new level. The state of DCD does not affect Transmitter operation, but must be low for the Receiver to operate. Registers Address bits A1 and A0 select the register to read/write. A1 A0 Write Read 0 0 Transmit Data Register Receiver Data Register 0 1 Programmed Reset Status Register 1 0 Command Register 1 1 Control Register The Programmed Reset does not cause any data transfer, but is used to clear the 6551 registers (data is "don't care") Control Register b3-b0 baud rate generator: 0000 : 16x external clock 0001 : 50 baud 0010 : 75 0011 : 110 0100 : 134.5 0101 : 150 0110 : 300 0111 : 600 1000 : 1200 1001 : 1800 1010 : 2400 1011 : 3600 1100 : 4800 1101 : 7200 1110 : 9600 1111 : 19,200 b4 receiver clock source 0 : external receiver clock 1 : baud rate generator b6,b5 word length 00 : 8 bits 01 : 7 10 : 6 11 : 5 b7 stop bits 0 : 1 stop bit 1 : 2 stop bits (1 stop bit if parity and word length = 8) (1 1/2 stop bits if word length = 5 and no parity) Command Register b0 Data Terminal Ready 0 : disable receiver and all interrupts (DTR high) 1 : enable receiver and all interrupts (DTR low) b1 Receiver Interrupt Enable 0 : IRQ interrupt enabled from bit 3 of status register 1 : IRQ interrupt disabled b3,b2 Transmitter Control Transmit Interrupt RTS level Transmitter 00 disabled high off 01 enabled low on 10 disabled low on 11 disabled low Transmit BRK b4 Normal/Echo Mode for Receiver 0 : normal 1 : echo (bits 2 and 3 must be 0) b5 Parity Enable 0 : parity disabled, no parity bit generated or received 1 : parity enabled b7,b6 Parity 00 : odd parity receiver and transmitter 01 : even parity receiver and transmitter 10 : mark parity bit transmitted, parity check disabled 11 : space parity bit transmitted, parity check disabled Status Register Status cleared by b0 Parity error * (1: error) self clearing ** b1 Framing error * (1: error) self clearing ** b2 Overrun * (1: error) self clearing ** b3 Receive Data Register Full (1: full) Read Receive Data Register b4 Transmit Data Reg Empty (1: empty) Write Transmit Data Register b5 DCD (0: DCD low, 1: DCD high) Not resettable, reflects DCD state b6 DSR (0: DSR low, 1: DCD high) Not resettable, reflects DSR state b7 IRQ (0: no int., 1: interrupt) Read Status Register note: * no interrupt generated for these conditions ** cleared automatically after a read of RDR and the next error free receipt of data